1. Field of the Invention
The invention relates in general to the design of integrated circuits, and more particularly, to testing of integrated circuit designs.
2. Description of the Related Art
As integrated circuits have become more and densely packed with gates, they have become progressively more difficult to test in order to ensure desired functionality. As a result, testability has become an increasingly more important and challenging goal of the integrated circuit design process. One approach to testing integrated circuit designs is to take a netlist representing an integrated circuit design and to add and/or replace certain storage elements such as flip-flops with special memory cells, called scan elements. Scan elements allow application of test vectors to certain portions of an integrated circuit produced according to the design.
An automatic test pattern generation (ATPG) process produces test vectors, also referred to as ATPG patterns. A suitable set of test vectors can demonstrate the absence of certain manufacturing faults. ATPG-style reasoning involves loading a test vector to a set of scan cells of an integrated circuit. The circuit performs one or more functional cycles so as to cause the stored test vector values to drive combinational logic to produce new values that are captured by the scan elements. The values stored in the scan elements after the one or more functional cycles are observed and compared with expected values to evaluate whether the circuit has a fault.
FIG. 1 is an illustrative drawing of a portion of an integrated circuit including two scan cells and generic combinational logic and showing shift and capture timing signals. A typical scan element comprises a dual purpose state element that can operate as a functional element in a circuit design during normal circuit operation, and alternatively, can operate as a unit of a serial scan-shift register during scan mode operation. In some embodiments, a scan element is implemented as an edge-triggered flip-flop with a two-way multiplexer (scan mux) to select between a system data D input (during function/capture mode operation) and scan-data SD input (during scan mode operation). The scan mux typically is controlled by a single control called a scan enable (SE) that selects between the scan-data (SD) and the system-data (D). Scan-data is transported from/to test equipment (not shown) by a serial shift operation. To that effect, the scan elements are connected into serial shift register strings called scan chains. It is not unusual for a scan chain to include hundreds or even thousands of individual scan elements, although only two are shown in this simplified illustrative drawing. The scan-in port of each scan cell in the chain is either connected to an external input (scan-in) for the first element in the chain or to the output of a single predecessor element in the chain. The output from the last scan element in the chain is connected to an external output (scan-out).
During scan mode operation, the SE control provides a logic value that causes the scan multiplexers to select the scan-data input (SD). For example, during first scan shift cycles control data (i.e. scan-in data) in the form of an ATPG pattern is serially shifted one bit at a time, from one scan element to the next in the chain. The scan-data follow scan data paths that bypass the combinational logic circuitry interposed between data paths between scan elements. Depending upon the length of the scan chain, hundreds or even thousands of clock cycles may be required to shift-in an entire ATPG pattern to the scan chain.
Once an entire ATPG pattern has been loaded into the scan chain, the scan cells typically operates for two clock cycles in a capture mode. The scan cells' SE control signals are changed to logic values that causes scan multiplexers to select the data input (D). A first clock cycle causes a scanned-in data value in a previous scan element in the chain to be provided to the combinational logic fed by that scan element. A second clock cycle causes a logic value generated by the combinational logic in response to the scanned-in control value to be captured on the D input of the next scan element in the chain.
For example, assume that the generic combinational logic includes an inverter circuit (not shown). Further assume that a value 0 was scanned in to the previous scan element. During the first clock pulse in the capture mode, the logic 0 value is provided to an input of the inverter. The inverter produces a logic value 1 in response to its logic 0 input. During the second scan cycle of the capture mode, the next scan element captures the logic 1 value.
Following the capture cycles, the SE control values are changed to cause the scan elements to select the scan-data (SD) input. During second shift cycles, the captured data values are shifted out of the scan chain for evaluation scn. It will be appreciated that testing ordinarily involves numerous different ATPG patterns used to test for numerous different potential design faults. In order to speed the testing process, a next ATPG pattern may be shifted in to the chain from test equipment, simultaneously with shift-out of previously captured (i.e. observed) data to the test equipment for evaluation. Thus, during the illustrated first scan shift cycles, while a new ATPG pattern is being shifted in to the scan chain, previously captured data may be shifted out for evaluation. Similarly, during second scan shift cycles, as the data captured in response to the first scanned-in data is shifted out, a next ATPG pattern can be shifted in.
Scan shift cycles ordinarily operate at a lower frequency than capture cycles. Scan shift cycles usually operate a frequency that is somewhat lower than the functional mode frequency of operation of the integrated circuit under test. Scan test is a structural test and not functional. Thus, there is no need to test it at-speed. Accordingly, the scan path need not be designed for at-speed operation as in the normal. (functional) mode it will never be used. In contrast, capture cycles typically operate at the normal functional mode operating frequency of the circuit under test. For this reason, the capture mode frequency often is referred to as being “at speed”.
Power distribution networks distribute power and ground voltages from pad locations to circuit blocks in a design. Shrinking device dimensions, faster switching frequencies and increasing power consumption in deep submicron technologies can cause large switching currents to flow in the power and ground networks, which degrade performance and reliability. Due to the resistance of the interconnects constituting the network, there is a voltage drop across the network, commonly referred to as IR drop. IR drop is a reduction in voltage that occurs on power supply networks (i.e. VDD) in integrated circuits.
Integrated-circuit design usually assumes the availability of an ideal power supply that can instantly deliver any amount of current to maintain the specified voltage throughout the chip. In reality, however, a combination of increasing current per-unit area on the die and narrower metal line widths (which causes an increase in the power-grid resistance) causes localized voltage drops within the power grid, leading to decreased power supply voltage at cells and transistors. These localized drops in the power supply voltage decrease the local operating voltage of the chip, potentially causing timing problems and functional failures.
IR drop can be both a local and global phenomena. IR drop can be local phenomenon when a number of cells in close proximity switch simultaneously, causing IR drop in that localized area. A higher power grid resistance to a specific portion of the chip can also Cause localized IR drop. IR drop can be a global phenomenon when activity in one region of a chip causes effects in other regions. For example, one logic block may suffer from IR drop because of the current drawn by another nearby logic block.
There can be an increased risk of IR drop during ATPG-style testing since the amount of simultaneous switching during a scan shift cycle may exceed the amount of switching expected during functional mode operation for which a chip was designed. The shifting of ATPG patterns or of captured (observed) test results through a scan chain can result in simultaneous switching of more gates than would ordinarily occur during actual functional mode operation of the chip. Moreover, causing the integrated circuit to perform “at speed” functional cycles with a scanned-in test pattern data also may lead to simultaneous switching of more gates than ordinarily would occur during actual functional mode operation of the chip.
One reason for this increased IR drop risk during manufacturing testing is that test patterns often are developed to perform structural testing without regard to the functional operation of the circuit. As such, improvidently selected test patterns may cause excessive switching during manufacturing testing that might never actually occur during functional operation of the chip. Thus, excessive switching during manufacturing testing can lead to IR drop problems or even thermal problems that suggest a design flaw when no flaw actually exists.
Thus, there has been a need to ensure that ATPG patterns do not themselves cause simultaneous switching that results in a significant risk of excessive IR drop and corresponding false detections of manufacturing faults. Aman A. Kokorady and C. P. Ravikumar, in “Static Verification of Test Vectors for IR Drop Failure”, ICCAD '03, pp. 760-764, address the problem of validation of a test vector for IR drop safeness using a technique, called “TestRail”. Flip-flops are assigned to a power rail, and a toggle activity factor is calculated using a formula that reflects both the toggling activity generated by a test vector and the stress it causes to the power rails. Kokorady et al. disclose the use of standard deviation techniques to find the most active patterns, and then subject them to detailed analysis. Kokorady's, however, teaches the use of VCD, which cannot easily be extended to shift cycles because the VCD are huge and processing for each shill cycle typically is beyond time and space complexities.
Nisar Ahmed et al., in “Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SoC Design”, DAC '07, pp. 533-538, address the detection of IR drop prone test patterns using a technique called Switching Capacitance Average Power (SCAP) model. The technique generates transition delay fault patterns considering the supply voltage noise. The SCAP model is used to account for both capacitances in the design and toggling activity. However, Nisar focused on capture cycles during at-speed test. While an IR drop may occur during shift cycles, the technique disclosed by Nisar is not easily extendable to shift cycles due to the time complexities.
Unfortunately, neither of these prior approaches takes into account physical characteristics of the power supply network such as density of the power grid or decoupling capacitance placement together with switching activity in attempting to evaluate whether ATPG patterns themselves are prone to cause excessive IR drop during scan shift. Therefore, there has been a need for improvements in the evaluation of test patterns for use in manufacturing testing. The present invention meets this need.